X-Message-Number: 26079
From: 
Date: Sun, 24 Apr 2005 11:04:17 EDT
Subject: Uploading (3.ii.0).   The synapse domain.

 Uploading (3.ii.0).
 
The synapse domain.
 
Most of the interneuron communications use the synapse architecture: At the 
end of an axon, a neurotransmitter is released and it activate some receptors 
on the facing dendrite spine head. this system works as an amplifier, there is 
one action potential on the axon side, it releases from one to seven vesicles, 
each with some thousand molecules and up to one hundred receptor can be 
activated.
 
Everything start with the action potential, an electrochemical signal with a 
very peculiar time shape. It  starts the release of vesicle storred against 
the axon membrane. Experiments have demonstrated that a rectangular electric 

signal produce the same effect. This is very important: It means that the shape
of the action potential is imposed by the way axons conduct the signal but has 
no information meaning. Any digital transmision could do the job.
 
An artificial brain will so use neurons without simulated axon and the axon 
tips will be simulated at the synapse unit linked to the dendrite receiving 
neuron.
 
One part of the learning is produced by a facilitation of the vesicle 

release. There is a number of release sites on the axon terminal, learning don't
act 
on this number, it works on the probability for each one to release at least 
one vesicle. this seems to be produced by expanding the number of cytofibrils 
bringing the vesicle from the "factory domain" to the membrane. This has two 
important consequences:
- In simulated synapses the simulated vesicle will be released with a 

probability P if there is an incoming action potential. Adjusting P will define 
the 
learning of the synapse.
- With imperfect conservation, the axon terminal may be destroyed in the 

original brain. Neverthless, we can define its memory value from the 
concentration 
of neurofibrils prensent.
 
The number of vesicles released is at most 7, so it may be defined with a 3 
bits number.
 
On the dendrite side, there may be up to one hundred receptors, learning 

don't act on their sensibility or number, so even if the spine head is destroyed
and we can't build back individual receptors, we can guess their rough number 
and this would be sufficient. For a given receptor kind, there could be a 

limited number of standard models so there is no need to describe individually 
each 
dendrite spine with its precise receptor number. From the decay products of 

the spine, a rough estimate of the number would be deduced and then the nearest
standard value would be used.
 
So what would be medelized?
- At the presynaptic level, the action potential is simulated by a 
rectangular electric signal.
- The number of  vesicle release site is standardized, with may be 8 sizes.
- The release probability P is computer controled and adjusted, it define the 
root memory process for the synapse. P is infered from the density of 
transport fibrils.
 - At the post synaptic level, the dendrite spine head is standardized, for a 
given kind and a given receptor there may be a 4 or 5 digits size 
definitions. 
- Because a single spine can have more than one receptor, the binary word 

used to define it must have a different frame for each receptor species. If for
example a neuron of the category xxxxxx can have four receptor kinds on its 

dendrites, each dendrite spine head would be defined by a 32 bits word. Bits 1 
to 
4 for receptor of the first kind, bits 5 to 8 for the second kind and so on.
 
The basic work is assumed to be done by some logic cells at FPGA level. This 
element must have 4 links with the outside:
- One programming, for the synapse complex loading from a memory.
- One input from the computer level to adjust P.
- One output to repport at computer level the number of firings in a given 
time lapse. This will be used to adjust P.
- One input for the action potential. The output goes to the dendrite tree 

and so don't need an output chanel outside the device. The global output goes to
the buffer and memory when the FPGA is rewired.
 
Yvan Bozzonetti.


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