X-Message-Number: 27560 From: Date: Thu, 2 Feb 2006 07:37:58 EST Subject: Uploading (3.iii.1) How much ressources ?. Uploading (3.iii.1) How much ressources ?. From time to time, I add to this message set about brain on electronics devices, the (3.x.y) subfamilly is more technology oriented. One preceeding conclusion was that some fast process must be worked out by FPGA and slower ones by computers. I would add another divide: Classical artificial neurons work only by firing or not. This is defined by the summed up potentials from postsynaptic domains. If this sum is larger than a threshold the neuron fire, if it is under it does nothing. There is a hidden assumption in this : A start, the neuron is at its equilibrium potential. In a real neuron this is a unlikely assumption because there are many subthreshold activities in many dendritic domains. This add up to a local, ie intraneuron, noise reducing the potential jump requested to fire. There is another general, ie interneuron, noise produced by electric gap juctions. In a microcolumn with up to some hundreds cells, the electrical links may be so strong that coordinated behavior may be the rule. On the onther side, from one microcolumn to another, most links seem to be done by axons. So the artificial model in current use would be a good fit for microcolumn links and a bad one for individual neurons in a given microcolumn. This give the idea to have two different electronics neurons: One equivalent to a biological one and another, a metaneuron, for a full microcolumn. In a first approximation, the metaneuron could be somewhat frozen in behavior, so it would give a defined answer to a given input. This would be actualised by the deeper simulation level, but this one would be done only on a sample of the information processed. Assume there is 10 billions neurons divided into 30 millions microcolumns. The brain simulator would use 30,000,000 metaneurons. If each is redefined one time every ten seconds, an electronics system able to work out a full microcolumn in 1 000 000 clock cycles could oversee five thousand metaneurons if it run at 500 MHz. This frequency seems the highest in current day FPGA. So, only six thousand such cards could handle the basic brain working at elementary level. This is somewhat optimistic as the rewiring time is not taken into account. The real value may be two to three times larger. Because the signal to a metaneuron needs to travel in something as 100 neurons, it can't be faster than one percent of the fastest signal in an individual neuron. If this is put at one millisecond, the metaneuron works at the 100 ms scale. This is indeed typical of the fastest reaction time in the brain. There must be a security margin: some signal may travel in a small subsample of a microcolumn. So the signal may be faster, particularly after training. The metaneuron may be actualised every ten miliseconds. Assume again 500 MHz clocking and 100 clock cycles to do the job on one metaneuron every 10 ms. 50,000 metaneurons could be simulated in a time sharing system. This would imply 600 chips for a full brain with 30 millions metaneurons. Again, this don't take into account the rewiring time. This can ask for x3 more material ressources. We have identified four processing here: The basic neuron fast current processed by a computer, the basic neuron slow one taken into account by an FPGA, the basic neuron local and global nonfiring activity, using gap junctions and the metaneuron, without gap junction nor slow/fast current division. In a first simulator, ASIC (custom made Application Specific Integrated Circuit) and TRACs must be put on the side, because they are too costly to produce and ask for too much work. That let only classical FPGAs and general purpose computers. Yvan Bozzonetti. Content-Type: text/html; charset="US-ASCII" [ AUTOMATICALLY SKIPPING HTML ENCODING! ] Rate This Message: http://www.cryonet.org/cgi-bin/rate.cgi?msg=27560